1. Technical Field
The disclosure relates generally to integrated circuit (IC) chip fabrication, and more particularly, to structures including a via having a refractory metal collar at a copper wire and dielectric layer liner-less interface, and a related method.
2. Background Art
In the integrated circuit (IC) chip fabrication industry, electromigration (EM) induced failure is a major concern for advanced back-end-of-line (BEOL) technology. Early EM induced failure, in particular, significantly reduces the projected current limit of product chip under operating conditions. One type of EM induced failure is referred to as “line-depletion.” As shown in FIGS. 1A-C, line-depletion EM includes electron current flowing from an upwardly extending via 10 down into a metal wire 12 below. As electron current flows, atoms move causing “slit void” failures 14 (FIG. 1C) initiating, for example, at a site 16 (FIG. 1B) between via 10 and a liner-less interface 18 between metal wire 12 and a dielectric layer 20 thereabove. It is well known that this slit void may cause very early fails under electromigration conditions during circuit operation, since it does not take much time to form such a small void. The arrows in FIGS. 1A and 1B show the direction of EM flux (i.e., the atom flow during electromigration). Typically, slit void failures 14 (FIG. 1C) start (or nucleate) at defective sites 16 (FIG. 1B) around an interface between via 10 and metal wire 12, and grow into a bottom 22 of via 10 until it extends over an entire interface and causes an electrical open 24, as depicted in FIG. 1C. Slit void failures 14 occur in both structures with (as shown) or without via gouging, i.e., where via 10 extends into metal wire 12.